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ISL43841
Data Sheet August 2004 FN6055.1
Low-Voltage, Single and Dual Supply, Dual 4 to 1 Multiplexer Analog Switch with Latch
The Intersil ISL43841 device is a precision, bidirectional, analog switches configured as a a dual 4 channel multiplexer/ demultiplexer designed to operate from a single +2V to +12V supply or from a 2V to 6V supply. The device has a latch bar pin to lock in the last switch address. ON resistance of 39 with a 5V supply and 125 with a +3.3V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 0.1nA at +25oC or 2.5nA at +85oC. All digital inputs have 0.8V to 2.4V logic thresholds, ensuring TTL/CMOS logic compatibility when using a single 3.3V or +5V supply or dual 5V supplies. The ISL43841 is a dual 4 to 1 multiplexer device. Table 1 summarizes the performance of this part.
TABLE 1. FEATURES AT A GLANCE CONFIGURATION 5V RON 5V tON/tOFF 12V RON 12V tON/tOFF 5V RON 5V tON/tOFF 3.3V RON 3.3V tON/tOFF Package 39 32ns/18ns 32 23ns/15ns 65 38ns/19ns 125 70ns/32ns 20 Ld 4x4 QFN DUAL 4:1 MUX
Features
* Fully Specified at 3.3V, 5V, 5V, and 12V Supplies for 10% Tolerances * ON Resistance (RON) Max, VS = 4.5V . . . . . . . . . . . 50 * ON Resistance (RON) Max, VS = +3V . . . . . . . . . . . 155 * RON Matching Between Channels, VS = 5V . . . . . . . . <2 * Low Charge Injection, VS = 5V . . . . . . . . . . . . . 1pC (Max) * Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V * Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . 2V to 6V * Fast Switching Action (VS = +5V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19ns * Guaranteed Max Off-leakage . . . . . . . . . . . . . . . . . . . . 2.5nA * Guaranteed Break-Before-Make * TTL, CMOS Compatible * Pb-free available
Applications
* Communications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems * Test Equipment - Medical Ultrasound - Magnetic Resonance Image - CT and PET Scanners (MRI) - ATE - Electrocardiograph * Audio and Video Signal Routing * Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches" * Application Note AN520 "CMOS Analog Multiplexers and Switches; Specifications and Application Considerations." * Application Note AN1034 "Analog Switch and Multiplexer Applications"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2004. All Rights Reserved
ISL43841 Pinout
ISL43841 (QFN) TOP VIEW
NO1B NO0B NO1A 16 15 NO2A 14 COMA 13 NO0A 12 NO3A LOGIC 6 -V 7 GND 8 ADD2B LOGIC 9 ADD1B 10 ADD2A 11 ADD1A N.C. 18
20 COMB NO3B NO2B LATCH A LATCH B 1 2 3 4 5
19
17
Truth Table (Note)
ISL43841 LATCH 0 1 1 1 1 ADD2 X 0 0 1 1 ADD1 X 0 1 0 1 SWITCH ON Last Switch Selected NO0 NO1 NO2 NO3
+V
Ordering Information
PART NO. (BRAND) ISL43841IR (43841IR) ISL43841IRZ (43841IR) (See Note) TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 20 Ld QFN 20 Ld QFN (Pb-free) PKG. DWG. # L20.4x4 L20.4x4
*Add "-T" suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
NOTE: Applies to either A or B switch. Logic "0" 0.8V. Logic "1" 2.4V, with V+ between 2.7V and 10V. X = Don't Care.
Pin Descriptions
PIN V+ VGND LATCH COM NO NC ADD N.C. FUNCTION Positive Power Supply Input Negative Power Supply Input. Connect to GND for Single Supply Configurations. Ground Connection Digital Control Input. Connect to +V for Normal Operation. Connect to GND to latch the last switch state. Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin Address Input Pin No Internal Connection
2
ISL43841
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V Input Voltages LATCH, NO, ADD (Note 1) . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . 30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) 20 Ld 4x4 QFN Package . . . . . . . . . . . . . . . . . . . . . 45 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead Tips Only)
Operating Conditions
Temperature Range ISL43841IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Signals on NO, COM, ADD, or LATCH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications: 5V Supply
Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 4) MIN TYP (NOTE 4) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full VS = 4.5V, ICOM = 2mA, VNO = 3V, (See Figure 6) VS = 4.5V, ICOM = 2mA, VNO = 3V, (Note 5) 25 Full 25 Full VS = 4.5V, ICOM = 2mA, VNO = 3V, 0V, (Note 6) VS = 5.5V, VCOM = 4.5V, VNO = +4.5V, (Note 7) 25 Full 25 Full VS = 5.5V, VCOM = 4.5V, VNO = +4.5V, (Note 7) 25 Full VS = 5.5V, VCOM = VNO = 4.5V, (Note 7) 25 Full
V-0.1 -2.5 -0.1 -2.5 -0.1 -2.5
44 1.3 7.5 0.002 0.002 0.002 -
V+ 50 80 4 6 9 12 0.1 2.5 0.1 2.5 0.1 2.5
V nA nA nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VLATCHH, VADDH Input Voltage Low, VLATCHL, VADDL Input Current, LATCHH, LATCHL, IADDH, IADDL DYNAMIC CHARACTERISTICS Address Transition Time, tTRANS VS = 4.5V, VNO = 3V, RL = 300, CL = 35pF, VIN = 0 to 3, (See Figure 1) VS = 5.5V, VNO = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 3) 25 Full Full 2 43 7 60 70 ns ns ns VS = 5.5V, VLATCHH, VADD = 0V or V+ Full Full Full 2.4 -0.5 0.03 0.8 0.5 V V A
Break-Before-Make Time, tBBM
3
ISL43841
Electrical Specifications: 5V Supply
Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS (See Figure 4) TEMP (oC) 25 Full Latch Hold Time, tH (See Figure 4) 25 Full Latch Pulse Width, tWPW (See Figure 4) 25 Full Charge Injection, Q NO/NC OFF Capacitance, COFF COM OFF Capacitance, COFF COM ON Capacitance, CCOM(ON) OFF Isolation Crosstalk, (Note 8) All Hostile Crosstalk, (Note 8) POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ VS = 5.5V, VLATCHH, VADD = 0V or V+, Switch On or Off Full 25 Full 25 Full NOTES: 3. VIN = logic voltage to configure the device in a given state. 4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. RON = RON (MAX) - RON (MIN). 6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC. 8. Between any two switches. 2 -1 -1 -1 -1 0.1 0.1 6 1 1 1 1 V A A A A CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) f = 1MHz, VNO = VCOM = 0V, (See Figure 8) f = 1MHz, VNO = VCOM = 0V, (See Figure 8) f = 1MHz, VNO = VCOM = 0V, (See Figure 8) RL = 50, CL = 15pF, f = 100kHz, VNO = 1VRMS, (See Figures 5 and 7) 25 25 25 25 25 25 25 (NOTE 4) MIN 25 35 0 0 15 25 TYP 0.3 3 12 18 92 110 -105 (NOTE 4) MAX UNITS 1 ns ns ns ns ns ns pC pF pF pF dB dB dB
PARAMETER Latch Setup Time, tS
Negative Supply Current, I-
Electrical Specifications + 12V Supply
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 4) MIN TYP (NOTE 4) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 10.8V, ICOM = 1.0mA, VNO = 9V, (See Figure 6) 25 Full
0 -0.1 -2.5
37
V+ 45 55
V nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
V+ = 10.8V, ICOM = 1.0mA, VNO = 9V, (Note 5)
25 Full
1.2 5 0.002 -
2 2 7 7 0.1 2.5
V+ = 10.8V, ICOM = 1.0mA, VNO = 3V, 6V, 9V, (Note 6)
25 Full
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF)
V+ = 13.2V, VCOM = 1V, 12V, VNO = 12V, 1V, (Note 7)
25 Full
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ISL43841
Electrical Specifications + 12V Supply
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS V+ = 13.2V, VCOM = 12V, 1V, VNO = 1V, 12V, (Note 7) TEMP (oC) 25 Full V+ = 13.2V, VCOM = 1V, 12V, VNO = 1V, 12V, or floating, (Note 7) 25 Full (NOTE 4) MIN -0.1 -2.5 -0.1 -2.5 TYP 0.002 0.002 (NOTE 4) MAX UNITS 0.1 2.5 0.1 2.5 nA nA nA nA
PARAMETER COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VLATCHH, VADDH Input Voltage Low, VLATCHL, VADDL Input Current, LATCHH, LATCHL, IADDH, IADDL DYNAMIC CHARACTERISTICS Address Transition Time, tTRANS V+ = 10.8V, VNO = 10V, RL = 300, CL = 35pF, VIN = 0 to 4, (See Figure 1) V+ = 13.2V, RL = 300, CL = 35pF, VNO = 10V, VIN = 0 to 4, (See Figure 3) (See Figure 4) 25 Full Full 25 Full Latch Hold Time, tH (See Figure 4) 25 Full Latch Pulse Width, tWPW (See Figure 4) 25 Full Charge Injection, Q OFF Isolation Crosstalk, (Note 8) All Hostile Crosstalk, (Note 8) NO or NC OFF Capacitance, COFF f = 1MHz, VNO = VCOM = 0V, (See Figure 8) COM OFF Capacitance, CCOM(OFF) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO = VCOM = 0V, (See Figure 8) f = 1MHz, VNO = VCOM = 0V, (See Figure 8) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 15pF, f = 100kHz, VNO = 1VRMS, (See Figures 5 and 7) 25 25 25 25 25 25 25 2 25 35 0 0 15 25 5 2.7 92 110 -105 3 12 18 27 50 55 5 ns ns ns ns ns ns ns ns ns pC dB dB dB pF pF pF V+ = 13.2V, VLATCHH, VADD = 0V or V+ Full Full Full 3.7 -0.5 3.3 2.7 0.03 0.8 0.5 V V A
Break-Before-Make Time Delay, tD Latch Setup Time, tS
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ Positive Supply Current, IV+ = 13.2V, VLATCHH, VADD = 0V or V+, all channels On or Off Full Full Full 2 -1 -1 12 1 1 V A A
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ISL43841
Electrical Specifications: 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 4) TYP MAX (NOTE 4) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 4.5V, ICOM = 1.0mA, VNO = 3.5V, (See Figure 6) 25 Full
0 -0.1 -2.5 -0.1 -2.5 -0.1 -2.5
81 2.2 11.5 0.002 0.002 0.002 -
V+ 90 120 4 6 17 24 0.1 2.5 0.1 2.5 0.1 2.5
V nA nA nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
V+ = 4.5V, ICOM = 1.0mA, VNO = 3V, (Note 5)
25 Full
V+ = 4.5V, ICOM = 1.0mA, VNO = 1V, 2V, 3V, (Note 6)
25 Full
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
V+ = 5.5V, VCOM = 1V, 4.5V, VNO = 4.5V, 1V, (Note 7)
25 Full
V+ = 5.5V, VCOM = 1V, 4.5V, VNO = 4.5V, 1V, (Note 7)
25 Full
V+ = 5.5V, VCOM = VNO = 4.5V, (Note 7)
25 Full
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VLATCHH, VADDH Input Voltage Low, VLATCHL, VADDL Input Current, LATCHH, LATCHL, IADDH, IADDL DYNAMIC CHARACTERISTICS Address Transition Time, tTRANS V+ = 4.5V, VNO = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 1) V+ = 5.5V, VNO = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 3) (See Figure 4) 25 Full Full 25 Full Latch Hold Time, tH (See Figure 4) 25 Full Latch Pulse Width, tWPW (See Figure 4) 25 Full Charge Injection, Q OFF Isolation Crosstalk, (Note 8) All Hostile Crosstalk, (Note 8) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 15pF, f = 100kHz, VNO = 1VRMS, (See Figures 5 and 7) 25 25 25 25 2 25 35 0 0 15 25 51 9 0.6 92 110 -105 70 85 1.5 ns ns ns ns ns ns ns ns ns pC dB dB dB V+ = 5.5V, VLATCHH, VADD = 0V or V+ Full Full Full 2.4 -0.5 0.03 0.8 0.5 V V A
Break-Before-Make Time, tBBM Latch Setup Time, tS
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ISL43841
Electrical Specifications: 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) MIN (NOTE 4) TYP MAX (NOTE 4) UNITS
PARAMETER POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+
Full V+ = 5.5V, V- = 0V, VLATCHH, VADD = 0V or V+, Switch On or Off 25 Full 25 Full
2 -1 -1 -1 -1
-0.1 -0.1 -
12 1 1 1 1
V A A A A
Positive Supply Current, I-
Electrical Specifications: 3.3V Supply
Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 4) TYP MAX (NOTE 4) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 3.0V, ICOM = 1.0mA, VNO = 1.5V, (See Figure 6) 25 Full
0 -0.1 -2.5 -0.1 -2.5 -0.1 -2.5
135 3.4 34 0.002 0.002 0.002 -
V+ 155 200 8 10 40 50 0.1 2.5 0.1 2.5 0.1 2.5
V nA nA nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
V+ = 3.0V, ICOM = 1.0mA, VNO = 1.5V, (Note 5)
25 Full
V+ = 3.0V, ICOM = 1.0mA, VNO = 0.5V, 1V, 2V, (Note 6)
25 Full
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
V+ = 3.6V, VCOM = 0V, 4.5V, VNO = 3V, 1V, (Note 7)
25 Full
V+ = 3.6V, VCOM = 0V, 4.5V, VNO = 3V, 1V, (Note 7)
25 Full
V+ = 3.6V, VCOM = VNO = 3V, (Note 7)
25 Full
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VLATCHH, VADDH Input Voltage Low, VLATCHL, VADDL Input Current, LATCHH, LATCHL, IADDH, IADDL DYNAMIC CHARACTERISTICS Address Transition Time, tTRANS V+ = 3.0V, VNO = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 1) V+ = 3.6V, VNO = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 3) (See Figure 4) 25 Full Full 25 Full Latch Hold Time, tH (See Figure 4) 25 Full 3 50 60 0 0 96 13 120 145 ns ns ns ns ns ns ns V+ = 3.6V, VLATCHH, VADD = 0V or V+ Full Full Full 2.4 -0.5 0.03 0.8 0.5 V V A
Break-Before-Make Time, tBBM Latch Setup Time, tS
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ISL43841
Electrical Specifications: 3.3V Supply
Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS (See Figure 4) TEMP (oC) 25 Full Charge Injection, Q OFF Isolation Crosstalk, (Note 8) All Hostile Crosstalk, (Note 8) POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 3.6V, V- = 0V, VLATCHH, VADD = 0V or V+, Switch On or Off Full 25 Full 25 Full 2 -1 -1 -1 -1 0.1 0.1 12 1 1 1 1 V A A A A CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 15pF, f = 100kHz, VNO = 1VRMS, (See Figures 5 and 7) 25 25 25 25 MIN (NOTE 4) 30 40 TYP 0.3 92 110 -105 MAX (NOTE 4) UNITS 1 ns ns pC dB dB dB
PARAMETER Latch Pulse Width, tWPW
Positive Supply Current, I-
Test Circuits and Waveforms
3V LOGIC INPUT 0V tTRANS VVNO0 SWITCH OUTPUT VOUT C 90% ADD1, 2 GND 0V 10% VNOX tTRANS LOGIC INPUT RL 300 CL 35pF V+ NO0 LATCH NO3 NO1, NO2 COM VOUT 50% tr < 20ns tf < 20ns V+ C C VC
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO) R + R L ( ON ) FIGURE 1B. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1A. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
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ISL43841 Test Circuits and Waveforms (Continued)
V+ C VC
3V LOGIC INPUT OFF ON 0V OFF RG 0 SWITCH OUTPUT VOUT Q = VOUT x CL VOUT VG LOGIC INPUT ADD1, 2 GND CL 1nF LATCH NO COM VOUT
FIGURE 2A. Q MEASUREMENT POINTS
Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2. CHARGE INJECTION
V+ tr < 20ns tf < 20ns
C
V-
C
3V LOGIC INPUT 0V
C LATCH V+ NO0-NO3 ADD1, 2 VOUT COM RL 300 CL 35pF
SWITCH OUTPUT VOUT 0V tBBM
80% LOGIC INPUT
GND
Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. tBBM MEASUREMENT POINTS FIGURE 3B. tBBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
tr < 20ns tf < 20ns 50%
tMPW LOGIC INPUT LATCH 3V 50% 0V tH tS 50%
V+
C
V-
C
C
NO1-NO3 tH ADD1, 2 LOGIC INPUT NO0 VOUT
V+
LOGIC INPUT ADDX
3V 50% 0V tON, tOFF 50%
LATCH LOGIC INPUT
GND
COM
RL 300
CL 35pF
VNOX SWITCH OUTPUT 0V
VOUT
90%
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO) R + R L ( ON ) FIGURE 4B. LATCH tS, tH, tMPW TEST CIRCUIT
FIGURE 4A. LATCH tS, tH, tMPW MEASUREMENT POINTS
FIGURE 4. LATCH SETUP AND HOLD TIMES
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ISL43841 Test Circuits and Waveforms (Continued)
V+ VV+ C V-
C
C
C
SIGNAL GENERATOR
LATCH NOX VNX 0V or V+ ADDX
RON = V1/1mA
LATCH NOX
1mA
V1
0V or V+ ADDX
ANALYZER RL
COMX
COMX GND
GND
FIGURE 5. OFF ISOLATION TEST CIRCUIT
FIGURE 6. RON TEST CIRCUIT
V+
C
V-
C
V+
C
V-
C
SIGNAL GENERATOR
LATCH NOA COMA
50
LATCH NOX
ADDX 0V or V+ NOB ANALYZER RL COMB GND IMPEDANCE ANALYZER N.C. COMX GND ADDX
0V or V+
FIGURE 7. CROSSTALK TEST CIRCUIT
FIGURE 8. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL43841 analog switch offers a precise switching capability from a bipolar 2V to 6V or a single 2V to 12V supply with low on-resistance (39) and high speed operation (tON = 38ns, tOFF = 19ns) with dual 5V supplies. It has an latch bar pin to lock in the last switch address. The device is especially well suited for applications using 5V supplies. With 5V supplies the performance (RON, Leakage, Charge Injection, ect.) is best in class. High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to V+(see Figure 9). To prevent forward biasing these diodes, V+ and V- must be applied before any input signals, and input signal voltages must remain between V+ and V-. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 9). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation.
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ISL43841
This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 9). These additional diodes limit the analog signal from 1V below V+ to 1V above V-. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no affect on logic thresholds. This switch family is TTL compatible (0.8V and 2.4V) over a V+ supply range of 2.7V to 10V. At 12V the VIH level is about 3.3V. This is still below the CMOS guaranteed high output minimum level of 4V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a VOH greater than 4V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS
OPTIONAL PROTECTION DIODE V+
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past 100MHz (see Figures 16 and 17). Figures 16 and 17 also illustrates that the frequency response is very consistent over varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch's input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 18 details the high Off Isolation and Crosstalk rejection provided by this family. At 10MHz, Off Isolation is about 55dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
1k
LOGIC VNO VCOM
VOPTIONAL PROTECTION DIODE
FIGURE 9. INPUT OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL43841 construction is typical of most CMOS analog switches, in that they have three supply pins: V+, V-, and GND. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the ISL43841 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (6V or 12V single supply), as well as room for overshoot and noise spikes. This switch device performs equally well when operated with bipolar or single voltage supplies.The minimum recommended supply voltage is 2V or 2V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance Curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and V-. One of these diodes conducts if any analog signal exceeds V+ or V-. Virtually all the analog leakage current comes from the ESD diodes to V+ or V-. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND.
11
ISL43841 Typical Performance Curves TA = 25oC, Unless Otherwise Specified
70 60 50 40 30 RON () 20 400 V- = 0V 300 200 100 0 V- = -5V VCOM = (V+) - 1V ICOM = 1mA 85oC 25oC -40oC RON () 120 110 100 90 80 70 60 50 90 80 70 60 50 40 30 60 50 40 -40oC 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 30 20 -5 -4 -3 -2 -1 1 0 VCOM (V) 2 3 4 5 -40oC ICOM = 2mA 85oC 25oC -40oC VS = 3V VS = 2V
85oC 25oC -40oC
85oC
25oC
25oC
85oC
VS = 5V
FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
60
225 200 175 150 125 100 75 160 140 120 100 80 60 100 90 80 70 60 50 40 0 85oC 25oC -40oC
ICOM = 1mA 55 50 V+ = 2.7V V- = 0V RON () 45
V+ = 12V V- = 0V
ICOM = 1mA
RON ()
85oC 40 35 30 25oC
85oC 25oC -40oC 85oC 25oC -40oC 1 3 2 VCOM (V) 4 5 V+ = 5V V- = 0V V+ = 3.3V V- = 0V
25 -40oC 20 0 2 4 6 VCOM (V) 8 10 12
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
300
FIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE
250 VCOM = (V+) - 1V 200
VCOM = (V+) - 1V V- = 0V
250
tRANS (ns)
tRANS (ns)
200
150
150
100
100
25oC 85oC
25oC 85oC -40oC 50 -40oC 0 2 3 4 5 6 7 8 V+ (V) 9 10 11 12 13 2 3
50 0
4 V (V)
5
6
FIGURE 14. ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE
FIGURE 15. ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE
12
ISL43841 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)
NORMALIZED GAIN (dB) VS = 5V 3 GAIN 0 -3 NORMALIZED GAIN (dB) VIN = 0.2VP-P to 5VP-P VS = 3V 3 GAIN 0 -3 VIN = 0.2VP-P to 4VP-P
PHASE (DEGREES)
PHASE
PHASE
45 90 135 180 RL = 50 1 10 100 FREQUENCY (MHz) 600
45 90 135 180 RL = 50 1 10 100 FREQUENCY (MHz) 600
FIGURE 16. FREQUENCY RESPONSE
FIGURE 17. FREQUENCY RESPONSE
-10 V+ = 3V to 12V or -20 VS = 2V to 5V RL = 50 -30 -40 CROSSTALK (dB) -50 -60 ISOLATION -70 CROSSTALK -80 -90 -100 ALL HOSTILE CROSSTALK -110 1k 10k 100k 1M 10M
10 20 30 OFF ISOLATION (dB) 40 50 60 70 80 90
3
2 V+ = 3.3V V- = 0V V+ = 12V V- = 0V V+ = 5V V- = 0V VS = 5V -2
1
0 Q (pC)
-1
-3 100 110 100M 500M -4 -5 -2.5 0 2.5 VCOM (V) 5 7.5 10 12
FREQUENCY (Hz)
FIGURE 18. CROSSTALK AND OFF ISOLATION
FIGURE 19. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 193 PROCESS: Si Gate CMOS
13
PHASE (DEGREES)
0
0
ISL43841 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L20.4x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VGGD-1 ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 5 0.25 0.35 1.95 1.95 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.50 BSC 0.60 20 5 5 0.60 12 0.75 0.15 2.25 2.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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